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LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 1 january 2013 LM555 single timer features high-current drive capability: 200 ma adjustable duty cycle temperature stability of 0.005%/c timing from s to hours turn off time less than 2 s applications precision timing pulse generation delay generation sequential timing ordering information part number operating temperature range top mark package packing method LM555cn 0 ~ +70c LM555cn dip 8l rail LM555cm LM555cm soic 8l rail LM555cmx LM555cm soic 8l tape & reel description the LM555 is a highly stable controller capable of pro- ducing accurate timing pulses. with a monostable opera- tion, the delay is controlled by one external resistor and one capacitor. with astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor. 8-dip 8-soic 1 1
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 2 block diagram figure 1. block diagram absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. th e absolute maximum ratings are stress ratings only. values are at t a = 25c unless otherwise noted. symbol parameter value unit v cc supply voltage 16 v t lead lead temperature (soldering 10s) 300 c p d power dissipation 600 mw t opr operating temperature range 0 ~ +70 c t stg storage temperature range -65 ~ +150 c f/f output stage 1 7 5 2 3 4 6 8 rrr comp. comp. discharging tr. vref vcc discharge threshold control voltage gnd trigger output reset gnd trigger output reset v cc discharge threshold control voltage threshold v ref discharging transistor
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 3 electrical characteristics values are at t a = 25c, v cc = 5 ~ 15 v unless otherwise specified. notes: 1. when the output is high, the supply current is typically 1 ma less than at v cc = 5 v. 2. tested at v cc = 5.0 v and v cc = 15 v. 3. these parameters, although guaranteed, are not 100% tested in production. 4. this determines the maximum value of r a + r b for 15 v operation, the maximum total r = 20 m , and for 5 v operation, the maximum total r = 6.7 m . parameter symbol conditions min. typ. max. unit supply voltage v cc 4.5 16.0 v supply current (low stable) (1) i cc v cc = 5 v, r l = 36 m a v cc = 15 v, r l = 7.5 15.0 ma timing error (monostable) initial accuracy (2) accur r a = 1 k to100 k c = 0.1 f 1.0 3.0 % drift with temperature (3) t / t5 0 p p m / c drift with supply voltage (3) t / v cc 0.1 0.5 % / v timing error (astable) initial accuracy (2) accur r a = 1 k to 100k c = 0.1 f 2.25 % drift with temperature (3) t / t 150 ppm / c drift with supply voltage (3) t / v cc 0.3 % / v control voltage v c v cc = 15 v 9.0 10.0 11.0 v v cc = 5 v 2.60 3.33 4.00 v threshold voltage v th v cc = 15 v 10.0 v v cc = 5v 3.33 v threshold current (4) i th 0.10 0.25 a trigger voltage v tr v cc = 5 v 1 . 1 01 . 6 72 . 2 0 v v cc = 15 v 4.5 5.0 5.6 v trigger current i tr v tr = 0 v 0.01 2.00 a reset voltage v rst 0.4 0.7 1.0 v reset current i rst 0.1 0.4 ma low output voltage v ol v cc = 15 v i sink = 10 ma 0.06 0.25 v i sink = 50 ma 0.30 0.75 v v cc = 5 v, i sink = 5 ma 0.05 0.35 v high output voltage v oh v cc = 15 v i source = 200 ma 12.5 v i source = 100 ma 12.75 13.30 v v cc = 5 v, i source = 100 ma 2.75 3.30 v rise time of output (3) t r 100 ns fall time of output (3) t f 100 ns discharge leakage current i lkg 20 100 na
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 4 application information table 1 below is the basic operating table of 555 timer. when the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold volt- age or the trigger voltage. only when the high signal is applied to the reset terminal, the timer's output changes accord- ing to threshold voltage and trigger voltage. when the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal dis- charge transistor turns on, lowering the threshold voltage to below 1/3 of the supply voltage. during this time, the timer output is maintained low. later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply volt- age, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output again at high. 1. monostable operation table 1. basic operating table reset (pin 4) v tr (pin 2) v th (pin 6) output (pin 3) discharging transistor (pin 7) low x x low on high < 1/3 v cc xh i g h o f f high > 1/3 v cc > 2/3 v cc low on high > 1/3 v cc < 2/3 v cc previous state figure2. monostable circuit figure 3. resistance and capacitance vs. time delay (t d ) figure 4. waveforms of monostable operation 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc r a c1 c2 r l trigger 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 m 1m 1 0k 100k r a = 1k capacitance(uf) time delay(s)
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 5 1. monostable operation figure 2 illustrates a monostable circuit. in this mode, the timer generates a fixed pulse whenever the tr igger voltage falls below v cc /3. when the trigger pulse voltage applied to the #2 pin falls below v cc /3 while the timer output is low, the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging the external capacitor c1 and setting the flip-flop output at the same time. the voltage across the external capacitor c1, v c1 increases exponentially with the time constant t = r a *c and reaches 2 v cc /3 at t d = 1.1 r a *c. hence, capacitor c1 is charged through resistor r a . the greater the time constant r a c, the longer it takes for the v c1 to reach 2 v cc /3. in other words, the time constant r a c controls the output pulse width. when the applied voltage to the capacitor c1 reaches 2 v cc /3, the comparator on the trigger terminal resets the flip- flop, turning the discharging transistor on. at this time, c1 begins to discharge and the timer output converts to low. in this way, the timer operating in the monostable repeats the above process. figure 3 shows the time constant rela- tionship based on r a and c. figure 4 shows the general waveforms during the monostable operation. it must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of v cc /3 before the timer output turns low. that is, although the output remains unaffected even if a different trigger pulse i s applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below v cc /3. figure 5 shows such a timer output abnormality. 2. astable operation figure 5. waveforms of monostable operation (abnormal) figure 6. a stable circuit figure 7. capacitance and resistance vs. frequency 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc r ac1 c2 r l r b 100m 1 10 100 1k 10k 100k 1e-3 0.01 0.1 1 10 100 10m 1m 100k 1 0k 1 k (r a +2r b ) capacitance(uf) frequency(hz)
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 6 an astable timer operation is achieved by adding resistor r b to figure 2 and configuring as shown on figure 6. in the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, op erat- ing as a multi-vibrator. when the timer output is high, its internal discharging transistor. turns off and the v c1 increases by exponential function with the time constant (r a +r b )*c. when the v c1 , or the threshold voltage, reaches 2 v cc /3; the comparator output on the trigger terminal becomes high, resetting the f/f and causing the timer output to become low. this turns on the discharging transis tor and the c1 discharges through the discharging channel formed by r b and the discharging transistor. when the v c1 falls below v cc /3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. the dis- charging transistor turns off and the v c1 rises again. in the above process, the section where the timer output is high is the time it takes for the v c1 to rise from v cc /3 to 2 v cc /3, and the section where the timer output is low is the time it takes for the vc1 to drop from 2 v cc /3 to v cc /3. when timer output is high, the equivalent circuit for charging capacitor c1 is as follows: since the duration of the timer output high state (t l ) is the amount of time it takes for the v c1 (t) to reach 2 v cc /3, figure 8. waveforms of astable operation vcc r a r b c1 vc1 (0-)=vcc/3 c 1 dv c1 dt ------------- v cc v0- () ? r a r b + ------------------------------- =1 () v c1 0+ () v cc 3 ? =2 () v c1 t () v cc 1 23 -- -e - t r a r b + () c1 ------------------------------------ - ? ?? ?? ? ?? ?? ?? ?? ?? ?? =3 () v c1 t () 23 -- -v cc v= cc 1 23 -- -e - t h r a r b + () c1 ------------------------------------ - ? ?? ?? ?? ? ?? ?? ?? ?? ?? ?? ?? =4 () t h c 1 r a r b + () in2 0.693 r a r b + () c 1 = =5 ()
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 7 the equivalent circuit for discharging capacitor c1, when timer output is low is, as follows: since the duration of the timer output low state (t l ) is the amount of time it takes for the vc1(t) to reach v cc /3, since r d is normally r b >>r d although related to the size of discharging transistor, t l = 0.693r b c 1 (10) consquently, if the timer operates in astable, the period is the same with 't = t h +t l = 0.693(ra+r b )c 1 +0.693r b c 1 = 0.693(r a +2r b )c 1 ' because the period is the sum of the charge time and discharge time. since frequency is the reciprocal of the period, the following applies: c1 r b r d v c1 (0-)=2vcc/3 c 1 dv c1 dt -------------- - 1 r a r b + ----------------------- v c1 0= +6 () v c1 t () 23 -- -v cc e - t r a r d + () c1 ------------------------------------ - =7 () --- 7 $ $ --- 7 $ $ f u - 3 " 3 % + () $ ------------------------------------ - = () u - $ 3 # 3 % + () *o 3 # 3 % + () $ = = () frequency, f 1 u -- - 1.44 r a 2r b + () c 1 --------------------------------------- - == 11 ()
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 8 3. frequency divider by adjusting the length of the timing cycle, the basic circuit of figure 1 can be made to operate as a frequency divider. figure 9. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. 4. pulse width modulation the timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and chang- ing the reference of the timer's internal comparators. figure 10 illustrates the pulse width modulation circuit. when the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated accord- ing to the signal applied to the control terminal. sine wave, as well as other waveforms, may be applied as a signal to the control terminal. figure 11 shows the example of pulse width modulation waveform. figure 9. waveforms of frequency divider operation figure 10. circuit for pulse width modulation figure 11. waveforms of pulse width modulation 8 4 7 1 2 3 5 6 cont gnd vcc disch thres reset trig out +vcc trigger r a c output input
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 9 5. pulse position modulation if the modulating signal is applied to the control terminal while the timer is connected for the astable operation, as in figure 12, the timer becomes a pulse position modulator. in the pulse position modulator, the reference of the timer's internal comparators is modulated, which modulates th e timer output according to the modulation signal applied to the control terminal. figure 13 illustrates a sine wave for modulation signal and the resulting output pulse position modulation; however, any wave shape be used . 6. linear ramp when the pull-up resistor ra in the monostable circuit shown in figure 2 is replaced with constant cur rent source, the v c1 increases linearly, generating a linear ramp. figure 14 shows the linear ramp generating circuit and figure 15 illus- trates the generated linear ramp waveforms. figure 12. circuit for pulse position modluation figure 13. wafeforms of pulse position modulation figure 14. circuit for linear ramp figure 15. waveforms of linear ramp 8 4 7 1 2 3 5 6 cont gnd vcc disch thres reset trig out +vcc r a c r b modulation output 1 5 6 7 8 4 2 3 reset vcc disch thres cont gnd out trig +vcc c2 r1 r2 c1 q1 output r e
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 10 in figure 14, current source is created by pnp transistor q1 and resistor r1, r2, and r e . for example, if v cc = 15 v, r e = 20 k , r1 = 5 k , r2 = 10 k , and v be = 0.7 v, v e =0.7 v+10 v=10.7 v, and i c =(15-10.7) / 20 k=0.215 ma. when the trigger starts in a timer configured as shown in figure 14, the current flowing through capaci tor c1 becomes a constant current generated by pnp transistor and resistors. hence, the v c is a linear ramp function as shown in figure 15. the gradient s of the linear ramp function is defined as follows: here the vp-p is the peak-to-peak voltage. if the electric charge amount accumulated in the capacitor is divided by the capacitance, the v c comes out as follows: v = q/c (15) the above equation divided on both sides by t gives: and may be simplified into the following equation: s = i/c (17) in other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using th e constant current flowing through the capacitor. if the constant current flow through the capacitor is 0.215 ma and the capacitance is 0.02 f, the gradient of the ramp function at both ends of the capacitor is s = 0.215 m / 0.022 = 9.77 v/ms. i c v cc v e ? r e --------------------------- =1 2 () here, v e is v e v be r 2 r 1 r 2 + --------------------- -v cc + =1 3 () s v pp ? u ---------------- =1 4 () v u --- - q u c ------------- =1 6 ()
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 11 physical dimensions figure 16. 8-lead, dip, jedec ms-001, 300" wide package drawings are provided as a service to customers considering fairchild components. drawings may chan ge in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the te rms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visit fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/products/discrete/pdf/8dip_tr.pdf . c 7 typ 7 typ .430 max [10.92] b a .400.373 [ 10.15 9.46 ] .250.005 [6.350.13] .036 [0.9 typ] .070.045 [ 1.781.14 ] .100 [2.54] .300 [7.62] .060 max [1.52] .310.010 [7.870.25] .130.005 [3.30.13] .210 max [5.33] .140.125 [ 3.553.17 ] .015 min [0.38] .021.015 [ 0.530.37 ] .010 +.005 -.000 [ 0.254 +0.127-0.000 ] pin #1 pin #1 (.032) [r0.813] (.092) [?2.337] top view option 1 top view option 2 .001[.025] c n08erevg c. does not include mold flash or protrusions. dambar protrusions shall not exceed d. does not include dambar protrusions. b. controling dimensions are in inches a. conforms to jedec registration ms-001, mold flash or protrusions shall not exceed variations bae. dimensioning and tolerancing notes: reference dimensions are in millimeters .010 inches or 0.25mm. .010 inches or 0.25mm. per asme y14.5m-1994. 8-dip
LM555 ? single timer ? 2002 fairchild semiconductor corporation www.fairchildsemi.com LM555 rev. 1.1.0 12 physical dimensions (continued) figure 17. 8-lead, soic,jedec ms-012, 150" narrow body package drawings are provided as a service to customers considering fairchild components. drawings may chan ge in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the te rms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visit fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/dwg/m0/m08a.pdf . 8-soic
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